From 42ec804cf15098f04ba22699392c583bf05d94d9 Mon Sep 17 00:00:00 2001 From: Saurav Singh Date: Sat, 20 Jun 2026 03:26:43 +0000 Subject: [PATCH 1/2] dbSta: keep top-level supply ports visible in pin iterator (#10414) write_verilog stopped emitting the "assign = ;" aliases that connect power/ground ports to an internal supply net whose name differs from the port name. This dropped the only representation of those connections in the Verilog netlist and broke LVS, even though the DB and DEF export were correct. Root cause: commit "dbsta: skip supply nets when iterating over pins" added supply-pin filtering to the top-instance branch of DbInstancePinIterator::hasNext(). The Verilog writer's writeAssigns() walks the top instance's pins to emit port/net aliases, so once supply BTerms were filtered out it never saw the power/ground ports and emitted no assigns. Fix: restore the pre-regression behavior of the top-instance branch so top-level block ports (the design's primary I/O, including power/ground pins) stay visible. Leaf instance iterm filtering is unchanged. Adds dbSta regression test write_verilog10 (two power ports + two ground ports each tied to a single supply net with a mismatched name) which fails before this change (no assigns emitted) and passes after. Signed-off-by: Saurav Singh --- src/dbSta/src/dbNetwork.cc | 23 +++++++++++------- src/dbSta/test/BUILD | 4 ++++ src/dbSta/test/CMakeLists.txt | 1 + src/dbSta/test/write_verilog10.def | 38 ++++++++++++++++++++++++++++++ src/dbSta/test/write_verilog10.ok | 29 +++++++++++++++++++++++ src/dbSta/test/write_verilog10.tcl | 12 ++++++++++ 6 files changed, 98 insertions(+), 9 deletions(-) create mode 100644 src/dbSta/test/write_verilog10.def create mode 100644 src/dbSta/test/write_verilog10.ok create mode 100644 src/dbSta/test/write_verilog10.tcl diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index b9e0884f1d0..9bbc91ebbaf 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -522,16 +522,21 @@ DbInstancePinIterator::DbInstancePinIterator(const Instance* inst, bool DbInstancePinIterator::hasNext() { if (top_) { - while (bitr_ != bitr_end_) { - dbBTerm* bterm = *bitr_; - if (!network_->isPGSupply(bterm)) { - next_ = network_->dbToSta(bterm); - bitr_++; - return true; - } - bitr_++; + // Do not filter supply BTerms here. The top-level block ports are the + // design's primary I/O (including power/ground pins) and must stay + // visible to consumers that walk the top instance's pins. In + // particular write_verilog relies on this iterator to emit the + // "assign = ;" aliases that connect a power/ground port to + // an internal supply net whose name differs from the port name. + // Filtering them out drops those connections and breaks LVS (#10414). + // Leaf instance terms are still filtered below. + if (bitr_ == bitr_end_) { + return false; } - return false; + dbBTerm* bterm = *bitr_; + next_ = network_->dbToSta(bterm); + bitr_++; + return true; } while (iitr_ != iitr_end_) { diff --git a/src/dbSta/test/BUILD b/src/dbSta/test/BUILD index c4c3f277999..7e6c923ed3e 100644 --- a/src/dbSta/test/BUILD +++ b/src/dbSta/test/BUILD @@ -81,6 +81,7 @@ ALL_TESTS = [ "write_verilog8", "write_verilog9", "write_verilog9_hier", + "write_verilog10", ] filegroup( @@ -286,6 +287,9 @@ filegroup( "write_verilog9_hier": [ "write_verilog9.v", ], + "write_verilog10": [ + "write_verilog10.def", + ], }.get(test_name, []), ) for test_name in ALL_TESTS diff --git a/src/dbSta/test/CMakeLists.txt b/src/dbSta/test/CMakeLists.txt index d3f659ed13c..f28f63385fa 100644 --- a/src/dbSta/test/CMakeLists.txt +++ b/src/dbSta/test/CMakeLists.txt @@ -71,6 +71,7 @@ or_integration_tests( write_verilog8 write_verilog9 write_verilog9_hier + write_verilog10 ) if(ENABLE_TESTS) diff --git a/src/dbSta/test/write_verilog10.def b/src/dbSta/test/write_verilog10.def new file mode 100644 index 00000000000..2a86d62166c --- /dev/null +++ b/src/dbSta/test/write_verilog10.def @@ -0,0 +1,38 @@ +VERSION 5.8 ; +NAMESCASESENSITIVE ON ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; + +DESIGN top ; + +UNITS DISTANCE MICRONS 1000 ; + +DIEAREA ( 0 0 ) ( 1000 1000 ) ; + + +COMPONENTS 1 ; +- u1 BUF_X1 ; +END COMPONENTS + +PINS 6 ; +- in1 + NET in1 + DIRECTION INPUT ; +- out1 + NET out1 + DIRECTION OUTPUT ; +- vccd1 + NET vdpwr + DIRECTION INPUT + USE POWER ; +- vccd2 + NET vdpwr + DIRECTION INPUT + USE POWER ; +- vssd1 + NET vgnd + DIRECTION INPUT + USE GROUND ; +- vssd2 + NET vgnd + DIRECTION INPUT + USE GROUND ; +END PINS + +SPECIALNETS 2 ; +- vgnd ( * vssd1 ) ( * vssd2 ) + + USE GROUND ; +- vdpwr ( * vccd1 ) ( * vccd2 ) + + USE POWER ; +END SPECIALNETS + +NETS 2 ; +- in1 ( PIN in1 ) ( u1 A ) ; +- out1 ( u1 Z ) ( PIN out1 ) ; +END NETS + +END DESIGN diff --git a/src/dbSta/test/write_verilog10.ok b/src/dbSta/test/write_verilog10.ok new file mode 100644 index 00000000000..45211765882 --- /dev/null +++ b/src/dbSta/test/write_verilog10.ok @@ -0,0 +1,29 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0128] Design: top +[INFO ODB-0130] Created 6 pins. +[INFO ODB-0131] Created 1 components and 4 component-terminals. +[INFO ODB-0132] Created 2 special nets and 0 connections. +[INFO ODB-0133] Created 2 nets and 2 connections. +module top (in1, + out1, + vccd1, + vccd2, + vssd1, + vssd2); + input in1; + output out1; + inout vccd1; + inout vccd2; + inout vssd1; + inout vssd2; + + wire vdpwr; + wire vgnd; + + BUF_X1 u1 (.A(in1), + .Z(out1)); + assign vccd1 = vdpwr; + assign vccd2 = vdpwr; + assign vssd1 = vgnd; + assign vssd2 = vgnd; +endmodule diff --git a/src/dbSta/test/write_verilog10.tcl b/src/dbSta/test/write_verilog10.tcl new file mode 100644 index 00000000000..a97b3e28e1a --- /dev/null +++ b/src/dbSta/test/write_verilog10.tcl @@ -0,0 +1,12 @@ +# Repro for issue #10414: multiple power/ground pins tied to one net +# whose name differs from the port names. write_verilog -include_pwr_gnd +# must emit assign statements linking each port to the net, otherwise the +# power connection is dropped and LVS breaks. +source "helpers.tcl" +read_lef Nangate45/Nangate45.lef +read_liberty Nangate45/Nangate45_typ.lib +read_def write_verilog10.def + +set verilog_file [make_result_file write_verilog10.v] +write_verilog -include_pwr_gnd $verilog_file +report_file $verilog_file From 26624fcbe2e9390745ab893fb5c99cc870d3adb7 Mon Sep 17 00:00:00 2001 From: Saurav Singh Date: Wed, 24 Jun 2026 04:39:24 +0000 Subject: [PATCH 2/2] dbSta: sort write_verilog10 dict entry lexicographically Move the write_verilog10 file-deps entry after write_verilog1 to satisfy buildifier's unsorted-dict-items check (BUILD:290). Addresses @maliberty review on #10723. Signed-off-by: Saurav Singh --- src/dbSta/test/BUILD | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/dbSta/test/BUILD b/src/dbSta/test/BUILD index 7e6c923ed3e..fb3186c36c4 100644 --- a/src/dbSta/test/BUILD +++ b/src/dbSta/test/BUILD @@ -270,6 +270,9 @@ filegroup( "write_verilog1": [ "reg1.def", ], + "write_verilog10": [ + "write_verilog10.def", + ], "write_verilog2": [ "reg4.def", ], @@ -287,9 +290,6 @@ filegroup( "write_verilog9_hier": [ "write_verilog9.v", ], - "write_verilog10": [ - "write_verilog10.def", - ], }.get(test_name, []), ) for test_name in ALL_TESTS