Kirann260

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Kirann260

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Verilog | VHDL |Digital Design | RISC-V | Vivado | ALTERA | QUARTUS | EDA Playground | FPGA | Learning RISC-V internals and contributing to open-source core

India

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Kirann260/README.md

Hi, I'm Kiran Meena

Verilog, Digital Design & RISC-V Enthusiast
FPGA + simulation practice (Vivado, EDA Playground)
Currently contributing to open-source RISC-V projects
Email: bee_2023022@iiitm.ac.in Check my contributions → riscv-contributions

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Kirann260 Kirann260 Public

1
serv serv Public

Forked from olofk/serv

SERV - The SErial RISC-V CPU

Verilog 1
single-cycle-riscv-processor single-cycle-riscv-processor Public

My "Single Cycle RISC-V Processor" project in Vivado

Verilog 1
ARM_CPU_Design ARM_CPU_Design Public

Verilog 1
Movie_Tracker Movie_Tracker Public

Movie Tracker is a C++ based console application that helps users manage and track movies using CSV files. It supports features like listing, adding, and organizing movie records efficiently. Ideal…

C++ 1
PRNG-CPLD-LVDS-Testing PRNG-CPLD-LVDS-Testing Public

Pseudo Random Pattern Generator on CPLD for LVDS Tx/Rx testing — VHDL, ModelSim, Quartus II

VHDL 1