Update dependency bitsandbytes to v0.50.0 - #17
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This PR contains the following updates:
==0.49.2→==0.50.0Release Notes
bitsandbytes-foundation/bitsandbytes (bitsandbytes)
v0.50.0: : Faster 4-bit inference, CPU/ROCm/Apple Silicon improvements, and more!Compare Source
This release brings a new fused 4-bit GEMM for inference on CUDA and ROCm, faster CPU ops on x86-64 and ARM64, reduced host-side overhead, and a much improved Apple Silicon backend. We've also added Windows on ARM CPU support, ROCm builds for Windows, additional ROCm and CUDA build variants, and new optimizer support on CPU and Intel XPU.
Highlights
🚀 New 4-bit GEMM kernels for inference (CUDA)
New fused 4-bit dequantize + GEMM kernels replace the old GEMV and
dequantize + F.linearpaths for small-to-medium batch sizes. 4-bit inference is up to 4x faster at batch sizes of 2 through 64 across Turing through Blackwell, with wins at batch size 1 in many cases too. Nested (double) quantization and bias are fused in as well, so nested quant sees an additional benefit. Kernel selection happens automatically at runtime based on shape, GPU architecture, and SM count. See #1949 for benchmarks and details.🚀 Fused 4-bit SIMT GEMM on ROCm
The SIMT version of the new 4-bit GEMM has been ported to ROCm and wired into the same dispatch for small inference batches, validated on gfx1100, gfx1201, and gfx1151 (#1979).
AMD ROCm improvements
Stability and performance improvements bring AMD ROCm support out of preview; it is now considered stable.
Apple Silicon (MPS)
Apple Silicon support is improved. The MPS backend added optimized Metal kernels from the Hub (#1875) and was substantially improved (#1960, #1983, #1994) so that all 4-bit and LLM.int8() configurations now work on MPS. On macOS 26+, install the
kernelspackage for the best performance, which enables the optimized Metal kernels; otherwise a naive fallback is used. The MPS path requires torch >= 2.9.The last remaining feature for support parity is the 8bit optimizers, which will land in a future release.
CPU performance on x86-64 and ARM64
Blockwise quantization and dequantization on CPU are considerably faster, mostly from better SIMD usage plus some compile flag tuning. Improvements range from 1.1x to over 20x depending on op, dtype, and hardware, with the largest gains on fp16 and on x86-64 CPUs without AVX-512. The LLM.int8() matmul on CPU was improved as well. See #1968 for benchmarks.
Reduced host-side CPU overhead
Reduced Python dispatch overhead, especially on the CUDA/ROCm backend (#1953).
Windows on ARM CPU support
Windows ARM64 CPU wheels are now built with NEON-optimized kernels (#1959), with nightly test coverage added (#1962).
New optimizer support
NVIDIA CUDA
Intel XPU
gemv_4bitbf16 correctness on Intel Arc A-series (Alchemist) GPUs (#1942).🚨 Breaking Changes
researchmodule, non-blockwise (block_wise=False) optimizers, and legacy dynamic quantization functions, along with their CUDA/HIP kernels (#1871, #1880).spmm_coo,spmm_coo_very_sparse) and dropped the cusparse/hipsparse dependencies (#1881).Deprecations
igemm,batched_igemm, andcheck_matmulare deprecated and now emit warnings (#2003).[in_features, out_features]orientation tomatmul_4bitnow emits aDeprecationWarning. Support is likely to be removed in the future. This is not a typical use case (#1949).Other improvements and bug fixes
This release also includes a number of other improvements, bug fixes, and documentation updates. See the full changelog below.
What's Changed
maxerr1threshold for fp32 intest_gemv_4bitby @jiqing-feng in #1919gemv_4bitbfloat16 correctness on Intel Arc A-series (Alchemist) GPUs by @jiqing-feng in #1942versionwhen loading CPUgemm_4bit_forwardfrom the Hub by @jiqing-feng in #1972New Contributors
Full Changelog: bitsandbytes-foundation/bitsandbytes@0.49.2...0.50.0
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