The current PyCoRAM can simulate a synthesized IP-core behavior by using Verilog simulators (such as Icarus Verilog and VCS). The user should write a test bench behavior in Verilog HDL.
The goal of this issue is to support Python PLI to write the test bench behavior in Python, not in Verilog HDL.
The current PyCoRAM can simulate a synthesized IP-core behavior by using Verilog simulators (such as Icarus Verilog and VCS). The user should write a test bench behavior in Verilog HDL.
The goal of this issue is to support Python PLI to write the test bench behavior in Python, not in Verilog HDL.