The current PyCoRAM accepts Verilog HDL source code as a computing logic description, in spite of a control-thread part can be written in Python.
The goal of this issue is to support Veriloggen (https://github.com/shtaxxx/veriloggen/) for writing a computing logic in python, as well as the control-thread.
The current PyCoRAM accepts Verilog HDL source code as a computing logic description, in spite of a control-thread part can be written in Python.
The goal of this issue is to support Veriloggen (https://github.com/shtaxxx/veriloggen/) for writing a computing logic in python, as well as the control-thread.