dbSta: keep top-level supply ports visible in pin iterator (#10414)

src/dbSta/src/dbNetwork.cc

@@ -522,16 +522,21 @@ DbInstancePinIterator::DbInstancePinIterator(const Instance* inst,
 bool DbInstancePinIterator::hasNext()
 {
   if (top_) {
-    while (bitr_ != bitr_end_) {
-      dbBTerm* bterm = *bitr_;
-      if (!network_->isPGSupply(bterm)) {
-        next_ = network_->dbToSta(bterm);
-        bitr_++;
-        return true;
-      }
-      bitr_++;
+    // Do not filter supply BTerms here.  The top-level block ports are the
+    // design's primary I/O (including power/ground pins) and must stay
+    // visible to consumers that walk the top instance's pins.  In
+    // particular write_verilog relies on this iterator to emit the
+    // "assign <port> = <net>;" aliases that connect a power/ground port to
+    // an internal supply net whose name differs from the port name.
+    // Filtering them out drops those connections and breaks LVS (#10414).
+    // Leaf instance terms are still filtered below.
+    if (bitr_ == bitr_end_) {
+      return false;
     }
-    return false;
+    dbBTerm* bterm = *bitr_;
+    next_ = network_->dbToSta(bterm);
+    bitr_++;
+    return true;
   }
 
   while (iitr_ != iitr_end_) {

src/dbSta/test/BUILD

@@ -81,6 +81,7 @@ ALL_TESTS = [
     "write_verilog8",
     "write_verilog9",
     "write_verilog9_hier",
+    "write_verilog10",
 ]
 
 filegroup(
@@ -269,6 +270,9 @@ filegroup(
             "write_verilog1": [
                 "reg1.def",
             ],
+            "write_verilog10": [
+                "write_verilog10.def",
+            ],
             "write_verilog2": [
                 "reg4.def",
             ],

src/dbSta/test/CMakeLists.txt

@@ -71,6 +71,7 @@ or_integration_tests(
     write_verilog8
     write_verilog9
     write_verilog9_hier
+    write_verilog10
 )
 
 if(ENABLE_TESTS)

src/dbSta/test/write_verilog10.def

@@ -0,0 +1,38 @@
+VERSION 5.8 ; 
+NAMESCASESENSITIVE ON ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+
+DESIGN top ;
+
+UNITS DISTANCE MICRONS 1000 ;
+
+DIEAREA ( 0 0 ) ( 1000 1000 ) ;
+
+
+COMPONENTS 1 ;
+- u1 BUF_X1 ;
+END COMPONENTS
+
+PINS 6 ;
+- in1 + NET in1 + DIRECTION INPUT ;
+- out1 + NET out1 + DIRECTION OUTPUT ;
+- vccd1 + NET vdpwr + DIRECTION INPUT + USE POWER ;
+- vccd2 + NET vdpwr + DIRECTION INPUT + USE POWER ;
+- vssd1 + NET vgnd + DIRECTION INPUT + USE GROUND ;
+- vssd2 + NET vgnd + DIRECTION INPUT + USE GROUND ;
+END PINS
+
+SPECIALNETS 2 ;
+- vgnd  ( * vssd1 ) ( * vssd2 )
+  + USE GROUND ;
+- vdpwr  ( * vccd1 ) ( * vccd2 )
+  + USE POWER ;
+END SPECIALNETS
+
+NETS 2 ;
+- in1 ( PIN in1 ) ( u1 A ) ;
+- out1 ( u1 Z ) ( PIN out1 ) ;
+END NETS
+
+END DESIGN

src/dbSta/test/write_verilog10.ok

@@ -0,0 +1,29 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0128] Design: top
+[INFO ODB-0130]     Created 6 pins.
+[INFO ODB-0131]     Created 1 components and 4 component-terminals.
+[INFO ODB-0132]     Created 2 special nets and 0 connections.
+[INFO ODB-0133]     Created 2 nets and 2 connections.
+module top (in1,
+    out1,
+    vccd1,
+    vccd2,
+    vssd1,
+    vssd2);
+ input in1;
+ output out1;
+ inout vccd1;
+ inout vccd2;
+ inout vssd1;
+ inout vssd2;
+
+ wire vdpwr;
+ wire vgnd;
+
+ BUF_X1 u1 (.A(in1),
+    .Z(out1));
+ assign vccd1 = vdpwr;
+ assign vccd2 = vdpwr;
+ assign vssd1 = vgnd;
+ assign vssd2 = vgnd;
+endmodule

src/dbSta/test/write_verilog10.tcl

@@ -0,0 +1,12 @@
+# Repro for issue #10414: multiple power/ground pins tied to one net
+# whose name differs from the port names.  write_verilog -include_pwr_gnd
+# must emit assign statements linking each port to the net, otherwise the
+# power connection is dropped and LVS breaks.
+source "helpers.tcl"
+read_lef Nangate45/Nangate45.lef
+read_liberty Nangate45/Nangate45_typ.lib
+read_def write_verilog10.def
+
+set verilog_file [make_result_file write_verilog10.v]
+write_verilog -include_pwr_gnd $verilog_file
+report_file $verilog_file