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[CHERIoT] Verify lockstep behavior for Ibex correctly identifies any faults injected into the new CHERIoT state or revoker

Status: Open.

#30657 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Guarantee that Ibex works as before when CHERIoT is disabled and ePMP is active

Status: Open.

#30656 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Validate bus errors and integrity errors are correctly dealt with in CHERIoT responses

Status: Open.

#30655 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Ensure the IF stage only fetches instructions it is allowed to fetch according to the PCC

Status: Open.

#30654 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Use directed tests to verify revocation correctly clears tag bits of revoked capabilities

Status: Open.

#30653 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Verify that Ibex can load/store capabilities and correctly set/clear the tag based on the interconnect's response

Status: Open.

#30652 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Adapt the cosim environment to work with the sail model by implementing our Ibex specific behaviors.

Status: Open.

#30651 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Make the golden model support CHERIoT. Since there is no riscv-isa-sim version with CHERIoT support, we suggest updating the cosim to use the CHERIoT sail model.

Status: Open.

#30650 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Generate functions to generate valid capabilities through capability modification sequences. We will need something like this for random/directed tests to not constantly fail with illegal capability modifications.

Status: Open.

#30649 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Add constraint logic for legal capability operand generation: for any instruction requiring a valid capability source, constrain the chosen register to one the tracker marks as tagged, in-bounds, and with the required permission bits set.

Status: Open.

#30648 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Extend register type to support capabilities where necessary

Status: Open.

#30647 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026

[CHERIoT] Modify behavior of existing instructions that work differently under CHERIoT (control flow, memory access, address construction)

Status: Open.

#30646 In lowRISC/opentitan;

· jayalp opened on Jul 3, 2026