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virt_support_gic: implement GICv3 delivery semantics - #4319

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Alex T Newman (alextnewman) wants to merge 8 commits into
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alextnewman:feature/virt-support-gicv3-delivery
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virt_support_gic: implement GICv3 delivery semantics#4319
Alex T Newman (alextnewman) wants to merge 8 commits into
microsoft:mainfrom
alextnewman:feature/virt-support-gicv3-delivery

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@alextnewman Alex T Newman (alextnewman) commented Aug 26, 2026

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What

Implement missing delivery semantics in OpenVMM's existing software GICv3:

  • priority masking, grouping, preemption, and active-priority state;
  • group gating, SPI affinity, and deterministic one-of-N routing;
  • EOIR/DIR completion, level/edge state, MSI pulses, and Group 0 FIQ versus Group 1 IRQ signaling.

Why

The current model can acknowledge disabled interrupts, ignore priority and affinity, mishandle priority writes, and lose asserted level state.

This fills those gaps according to Arm IHI 0069H.b without adding another interrupt-controller backend. Architectural definitions remain in aarch64defs, GIC state remains in virt_support_gic, and virt_hvf only connects platform geometry and interrupt outputs.

Testing

  • clippy, rustdoc, and cargo xtask fmt;
  • 49 GIC tests, 8 HVF tests, an MSI regression test, and a deterministic CPU-interface model;
  • 4-vCPU ARM64 Linux UEFI boot to multi-user with all CPUs online;
  • Arm VBSA Architecture Compliance Suite.

Arm VBSA

As an external check, I booted Arm's released VBSA ACS v26.03 (Vbsa.efi, suite version 1.0.0) as a UEFI payload on the exact signed 4-vCPU build. The artifact, firmware, media layout, topology, and selected rules were pinned across the retained control and candidate runs.

The GIC module and V_L1GI_01/V_L1PP_00 rules discover all four PEs and the GICv3 platform. GICv3 identification, non-secure SGI delivery, and the virtual-timer PPI pass.

VBSA is independent integration evidence, but it does not cover most of the priority, affinity, one-of-N, active-priority, or EOImode state changed here. Those claims remain anchored to Arm IHI 0069H.b and focused tests. No Arm binaries or test harnesses are added to OpenVMM.

Boundaries

This does not add MBI/ITS/LPI, physical timers, reset/save-restore, RangeSelector, or GICD pending-register writes. One-of-N uses a deterministic first-eligible policy, and no performance improvement is claimed.

Alex T Newman and others added 7 commits August 26, 2026 08:58
Model the banked CPU-interface state, priority masking, binary points, active priorities, group gating, and interrupt selection needed for architectural acknowledge and preemption.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Copilot-Session: ba714a8a-7d9a-4f49-8664-6526bb77a44a
Route shared interrupts by affinity or deterministic one-of-N selection and implement combined or split priority-drop/deactivation semantics for SGIs, PPIs, and SPIs.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Copilot-Session: ba714a8a-7d9a-4f49-8664-6526bb77a44a
Mask unimplemented priority bits, report the implemented ICC_CTLR_EL1 capabilities, and compare the single-PE CPU-interface state machine against a deterministic independent-state model.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Copilot-Session: ba714a8a-7d9a-4f49-8664-6526bb77a44a
Size distributor state and GICD_TYPER from the platform topology so delivery and register bounds agree with the guest-visible interrupt range.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Copilot-Session: ba714a8a-7d9a-4f49-8664-6526bb77a44a
Apply specification-cited level/edge state, group and one-of-N eligibility, cross-group preemption, deactivation wakeups, and lock-atomic SPI acknowledge behavior.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Copilot-Session: ba714a8a-7d9a-4f49-8664-6526bb77a44a
Drive Group 0 through FIQ and Group 1 through IRQ, wake all possible targets after configuration changes, and tie the software GIC geometry to the landed HVF platform.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Copilot-Session: ba714a8a-7d9a-4f49-8664-6526bb77a44a
Remove deferred reset coupling, reuse the landed VP wake contract, centralize architectural encodings and atomic subword handling, preserve MSI pulse semantics, bound guest-controlled private IDs and SGI affinity, strengthen tests, and document model scope.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Copilot-Session: ba714a8a-7d9a-4f49-8664-6526bb77a44a
@alextnewman
Alex T Newman (alextnewman) requested a review from a team as a code owner August 26, 2026 17:40
Copilot AI lite review requested due to automatic review settings August 26, 2026 17:40
@github-actions github-actions Bot added the unsafe Related to unsafe code label Aug 26, 2026
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⚠️ Unsafe Code Detected

This PR modifies files containing unsafe Rust code. Extra scrutiny is required during review.

For more on why we check whole files, instead of just diffs, check out the Rustonomicon

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Pull request overview

This PR enhances OpenVMM’s ARM GICv3 path by implementing more accurate interrupt delivery semantics in the software GIC model (virt_support_gic), and by updating platform plumbing (notably HVF) and MSI delivery to align with edge/pulse behavior and Group0/Group1 signaling.

Changes:

  • Add SPI “pulse” delivery to distinguish edge-like MSI delivery from level assertions (ControlGic::pulse_spi_irq) and switch v2m/MSI paths to use it.
  • Substantially extend the software GICv3 model with priority masking/grouping, preemption/active-priority tracking, routing (affinity + deterministic one-of-N), and split completion (EOIR/DIR), plus broad test coverage including a deterministic differential model.
  • Update HVF integration to configure the distributor with the correct SPI count and to drive independent FIQ (Group 0) and IRQ (Group 1) pending signals.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 1 comment.

Show a summary per file
File Description
vmm_core/virt/src/irqcon.rs Extends ControlGic with pulse_spi_irq for edge-like SPI delivery.
vmm_core/virt/src/aarch64/gic_v2m.rs Switches v2m MSI delivery from SPI assert to SPI pulse semantics.
vmm_core/virt/src/aarch64/gic_software_device.rs Uses SPI pulses for MSI delivery and adds a unit test validating pulse usage.
vmm_core/virt_support_gic/src/model_tests.rs Adds a deterministic differential model test for CPU-interface state machine behavior.
vmm_core/virt_support_gic/src/lib.rs Implements missing GICv3 delivery semantics (routing, priority, gating, EOImode) and extensive unit tests.
vmm_core/virt_hvf/src/lib.rs Updates HVF GIC wiring for correct SPI count, pulse support, and separate Group0/Group1 interrupt signaling.
vm/aarch64/aarch64defs/src/lib.rs Adds shared GIC constants (private count, special/spurious INTIDs).
vm/aarch64/aarch64defs/src/gic.rs Adds GICD_IROUTER and ICC_CTLR_EL1 bitfield definitions used by the model.

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Comment thread vmm_core/virt/src/irqcon.rs
Assert and deassert the default host-backed SPI line for message-signaled delivery, while preserving the software GIC override that latches Pending without line state.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Copilot-Session: ba714a8a-7d9a-4f49-8664-6526bb77a44a
Copilot AI review requested due to automatic review settings August 26, 2026 17:56

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Pull request overview

Copilot reviewed 8 out of 8 changed files in this pull request and generated no new comments.

@alextnewman

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I am converting this PR to a draft pending the result of #4289 , which takes a different path and would require us to take a different approach for hvf.

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